Flash memory is a type of electronic memory media that can hold its data in the absence of operating power. Flash memory can be programmed, erased, and reprogrammed during its useful life (which may be up to one million write cycles for typical flash memory devices). Flash memory is becoming increasingly popular as a reliable, compact, and inexpensive nonvolatile memory in a number of consumer, commercial, and other applications. As electronic devices get smaller and smaller, it becomes desirable to increase the amount of data that can be stored per unit area on an integrated circuit memory element, such as a flash memory unit. In this regard, one conventional flash memory technology is based upon a memory cell that utilizes a charge trapping dielectric element that is capable of storing two bits of data. In such an arrangement, one bit can be stored using a first charge storing region on one side of the charge trapping dielectric element, while a second bit can be stored using a second charge storing region on the other side of the charge trapping dielectric element.
FIG. 1 is a cross sectional view of a conventional dual bit memory cell 100. Memory cell 100 includes a silicon nitride layer 102 and a P-type semiconductor substrate 104 having a first buried junction region 106 and a second buried junction region 108. First buried junction region 106 and second buried junction region 108 are each formed from an N+ semiconductor material. Silicon nitride layer 102 is sandwiched between two layers of silicon oxide (identified by reference numbers 110 and 112).
Overlying silicon oxide layer 110 is a polysilicon gate 114. Gate 114 is doped with an N-type impurity (e.g., phosphorus). Memory cell 100 is capable of storing two data bits: a left bit represented by the dashed circle 116; and a right bit represented by the dashed circle 118. In practice, memory cell 100 is generally symmetrical and first buried junction region 106 and second buried junction region 108 are interchangeable. In this regard, first buried junction region 106 may serve as the source region with respect to the right bit 118, while second buried junction region 108 may serve as the drain region with respect to the right bit 118. Conversely, second buried junction region 108 may serve as the source region with respect to the left bit 116, while first buried junction region 106 may serve as the drain region with respect to the left bit 116.
Practical devices include a very large number of memory cells in an array architecture having wordlines that correspond to the gates of the memory cells and bitlines that correspond to the sources and drains of the memory cells. Control logic and circuitry for the array architecture governs the selection of memory cells, the application of voltage to the wordlines, and the application of voltage to the bitlines during conventional flash memory operations, such as: programming; reading; erasing; and soft programming.
Programming of memory cell 100 can be accomplished by known hot electron injection techniques (also known as channel hot electron or CHE programming). In accordance with conventional programming techniques, the right bit 118 is programmed by applying a relatively high programming voltage to gate 114 via the appropriately selected wordline, grounding the bitline corresponding to first buried junction region 106 (which serves as the source in this case), and applying a relatively high drain bias voltage to the bitline corresponding to second buried junction region 108 (which serves as the drain in this case). Conversely, the left bit 116 is programmed by applying a relatively high programming voltage to gate 114 via the appropriately selected wordline, grounding the bitline corresponding to second buried junction region 108 (which serves as the source in this case), and applying a relatively high drain bias voltage to the bitline corresponding to first buried junction region 106 (which serves as the drain in this case).
Erasing of memory cell 100 can be accomplished by applying a relatively high negative erase voltage (e.g., −5.0 volts) to gate 114 via the appropriately selected wordline, and applying relatively high source and drain bias voltages (e.g., 5.0 volts) to the corresponding bitlines. Such erasing is intended to leave both bits of memory cell 100 in an erased or unprogrammed state. Flash memory arrays typically include sectors of many individual memory cells, and the cells are often erased on a sector-by-sector basis. In other words, all of the bits in a given sector are erased before the erase operation proceeds to the next sector. An erase verify operation may be performed following an erase operation to test whether all of the bits in the sector are actually erased.
An erase verification operation is similar to the programming operations mentioned above, however, lower wordline voltages and lower bitline bias voltages are applied. The goal of an erase verification operation is to determine whether the threshold voltage (VT) of the target memory cell is within a desired range corresponding to an acceptable erase state. The erase verification operation generates a very low verification current in the target memory cell and compares the verification current to a reference current generated by a reference memory cell.